The present invention is directed, in general, to semiconductor fabrication and, more specifically, to a gallium arsenide metal-oxide semiconductor field effect transistor (GaAs MOSFET) having low capacitance and on-resistance and method of manufacturing the same.
Power conversion circuitry commonly employed in a variety of electronic circuits. Integrated circuits (ICs) are no exception and large demand for improved functionality and enhanced performance continues to increase. In an effort to meet these demands, the IC industry continues to decrease the size of component devices to place more circuits in the same amount of space. Over the last several years, structures have diminished from 1.2 xcexcm gate areas to gate areas of 0.25 xcexcm and promise to become even smaller in the future.
The ever-increasing demand for smaller components places strict operating constraints on individual devices. As power converter circuitry continues to shrink, minimizing the factors that increase both the resistance and the total capacitance of the power switching device becomes critical.
Currently, power switching devices built on silicon suffer from such resistance and capacitance problems, which limit further improvement. The resistance of the silicon substrate is inherently higher than desired. Furthermore, the vertical structuring of the layers from which such devices are composed causes high channel resistance and undesirable drift region resistance. For instance, as circuit integration approaches the 0.5 xcexcm level, the drift resistance between source and drain regions of the device is the dominant performance limiting factor.
However, when low blocking-voltage, typically less than 100 V, designs are desired, the channel resistance also becomes a significant portion of the overall device resistance. Therefore, if drift resistance can be reduced, power switching devices having reduced channel resistance will also be required for low-voltage applications. Channel resistance appears to be limited by the characteristics of the gate oxide interface. High temperature annealing steps produce a rough interface between the oxide and underlying doped regions. Much effort has been expended in the search for processes that reduce the interface irregularities. Also, gate oxide materials having inherently better interface characteristics have been sought. Such efforts have met with moderate success as evidenced by the limitations of current state-of-the-art devices.
Accordingly, what is needed in the art is a device for power switching applications that has improved drift and channel resistance profiles and method of manufacturing the same.
To address the above-discussed deficiencies of the prior art, the present invention provides a MOSFET, a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions. In this application, the term xe2x80x9claterally straddlingxe2x80x9d means being located on both sides of.
The present invention therefore introduces the broad concept of structuring a MOSFET laterally, such that its channel resistance, and therefore its input and output capacitances and on-resistance, are reduced. In an embodiment to be illustrated and described, the substrate employed to fabricate a MOSFET according to the principles of the present invention comprises gallium arsenide.
In one embodiment of the present invention, the epitaxial layer is beryllium-doped. Those skilled in the pertinent art will understand that other conventional P-type or N-type dopants fall within the broad scope of the present invention.
In one embodiment of the present invention, the gate oxide layer comprises gallium III oxide. In an embodiment to be illustrated and described, the gate oxide layer is formed by way of electron beam evaporation from a single-crystal source.
In one embodiment of the present invention, the drift, drain and source regions comprise a silicon dopant. Those skilled in the pertinent art will understand that other conventional N-type dopants fall within the broad scope of the present invention.
In one embodiment of the present invention, the MOSFET further includes an N layer located in the epitaxial layer and between the gate region and the gate oxide layer. The N layer is preferably doped such that, at zero bias, a first depletion region within the N layer proximate the gate region contacts a second depletion region within the N layer proximate the gate oxide layer.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.